Remotely testable setup of soft CPU with cryptographic TRNG coprocessor extension embedded into Altera FPGA

Proposed setup provides complete design for remote testing of custom configurable TRNG coprocessor. The coprocessor is connected to the standard Altera Nios soft CPU embedded into Altera Cyclone III FPGA. Parameterized TRNG design is provided in VHDL and its main design parameters can be modified by end user. Nios CPU software evaluates online quality of generated random bit stream by using standard FIPS140 statistical tests. Complete design uses Nios II Cyclone III embedded evaluation kit board and additional configuration, debug and monitoring interfaces prepared for remotely accessible infrastructure of new European Digital Virtual Design (eDiViDe) project infrastructure. Proposed setup and eDiViDe infrastructure enable remote evaluation and testing of proposed complete demonstration of TRNG design. Moreover, the end user can use provided infrastructure and remotely test even its own TRNG design submitted in VHDL code.