Title :
Challenges in the characterization and modeling of BTI induced variability in metal gate / High-k CMOS technologies
Author :
Kerber, Andreas ; Nigam, Tanya
Author_Institution :
Technol. Reliability Dev., GLOBALFOUNDRIES Inc., Yorktown Heights, NY, USA
Abstract :
Large scale BTI data was collected on discrete MG/HK devices to discuss modeling challenges related to BTI induced variability. A fast, parallel BTI testing procedure is introduced. This utilizes the PCI card characterization methodology to highlight a close link between BTI variability and RDF, and to discuss the impact of BTI recovery and wafer-to-wafer variation on the BTI statistics. We demonstrate a correlation between time-zero VT and ΔVT and illustrate the minor impact of BTI induced variability on post-stress VT distributions relevant for modeling the circuit aging.
Keywords :
CMOS integrated circuits; high-k dielectric thin films; integrated circuit testing; negative bias temperature instability; semiconductor device models; BTI induced variability characterization; BTI induced variability modeling; PCI card characterization methodology; RDF; discrete MG-HK devices; metal gate-high-k CMOS technologies; parallel BTI testing procedure; wafer-to-wafer variation; Data models; Earth Observing System; Gaussian distribution; Logic gates; Random access memory; Semiconductor device modeling; Stress; BTI variability; CMOS; SRAM; high-k dielectrics; metal gate;
Conference_Titel :
Reliability Physics Symposium (IRPS), 2013 IEEE International
Conference_Location :
Anaheim, CA
Print_ISBN :
978-1-4799-0112-8
Electronic_ISBN :
1541-7026
DOI :
10.1109/IRPS.2013.6531959
