Title :
Workload dependent NBTI and PBTI analysis for a sub-45nm commercial microprocessor
Author :
Mintarno, E. ; Chandra, Vishal ; Pietromonaco, David ; Aitken, Robert ; Dutton, R.W.
Author_Institution :
Stanford Univ., Stanford, CA, USA
Abstract :
This paper analyzes aging effects on various design hierarchies of a sub-45nm commercial processor running realistic applications. Dependencies of aging effects on switching-activity and power-state of workloads are quantified. This paper presents an “instance-based” simulation flow, which creates a standard-cell library for each use of the cell in the design, by aging each transistor individually. Implementation results show that processor timing degradation can vary from 2% to 11%, depending on workload. Lifetime computational power efficiency improvements of optimized self-tuning is demonstrated, relative to a one-time worst-case guardbanding approach.
Keywords :
ageing; circuit simulation; circuit tuning; microprocessor chips; switching circuits; transistors; NBTI analysis; PBTI analysis; commercial microprocessor; instance-based simulation flow; lifetime computational power efficiency improvement; negative bias temperature instability; one-time worst-case guardbanding approach; positive bias temperature instability; power-state workload; self-tuning optimization; size 45 nm; standard-cell library; switching-activity effect; timing degradation; transistor aging; Aging; Degradation; Delays; Libraries; Logic gates; Transistors;
Conference_Titel :
Reliability Physics Symposium (IRPS), 2013 IEEE International
Conference_Location :
Anaheim, CA
Print_ISBN :
978-1-4799-0112-8
Electronic_ISBN :
1541-7026
DOI :
10.1109/IRPS.2013.6531971
