Error-prediction analyses in 1X, 2X and 3Xnm NAND flash memories for system-level reliability improvement of solid-state drives (SSDs)

Author

Tanakamaru, Shuhei ; Doi, M. ; Takeuchi, Ken

Author_Institution

Dept. of Electr., Electron., & Commun. Eng., Chuo Univ., Tokyo, Japan

fYear

2013

fDate

14-18 April 2013

Abstract

The system-level reliability of solid-state drives (SSDs) is investigated with 1X, 2X and 3Xnm NAND flash memories. The reliability degradation of NAND with scaling is an serious issue. Advanced ECC with signal processing such as error-prediction low-density parity-check (EP-LDPC) and error recovery (ER) scheme will be needed in the future SSDs. In this paper, the NAND reliability information used for EP-LDPC and ER is examined. System-level reliability with conventional ECC and EP-LDPC is measured.

Keywords

NAND circuits; flash memories; integrated circuit reliability; parity check codes; 1X NAND flash memories; 2X NAND flash memories; 3Xnm NAND flash memories; EP-LDPC; ER scheme; NAND reliability degradation; NAND reliability information; SSD; advanced ECC; error recovery scheme; error-prediction analysis; error-prediction low-density parity-check; signal processing; solid-state drives; system-level reliability improvement; Bit error rate; Computer architecture; Erbium; Error correction codes; Flash memories; Parity check codes; Reliability; ECC; LDPC; NAND flash memory; error-correcting code; low-density parity-check;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium (IRPS), 2013 IEEE International

Conference_Location

Anaheim, CA

ISSN

1541-7026

Print_ISBN

978-1-4799-0112-8

Electronic_ISBN

1541-7026

Type

conf

DOI

10.1109/IRPS.2013.6531979

Filename

6531979