DocumentCode :
608175
Title :
A junction leakage mechanism and its effects on advance SRAM failure
Author :
Maji, D. ; Liao, P.J. ; Lee, Young-Hyun ; Shih, J.R. ; Chen, S.C. ; Gao, S.H. ; Lee, J.H. ; Wu, Kaijie
Author_Institution :
Taiwan Semicond. Manuf. Co., Ltd., Hsinchu, Taiwan
fYear :
2013
fDate :
14-18 April 2013
Abstract :
Junction leakage is becoming an important reliability concern as shallow trench isolation (STI) continues to scale down. This junction leakage has to be considered to improve SRAM Vccmin degradation. The major index of junction leakage in SRAM cell is found to be off-state leakage current as the leakage phenomenon externally manifests as a current flow from butted contact (BCT) to lower pull down (LPD) transistor gate. Isolation test patterns (P+/N-well to P-Well) with well photo misalignments are designed to verify Si/STI interface damage effect on junction leakage. Process experiment with PW misalignment shows isolation leakage current (P+ to PW) increase after electrical stress. However, this type of leakage due to PW misalignment shows weak temperature and voltage dependence, indicating that the trap-assisted carrier hopping at STI Si/SiO2 interface and the PW misalignment are paramount of SRAM junction reliability. Using TCAD simulation, we have verified that carriers transport through the Si/STI interface traps along with poor PW misalignment is the root causes of the junction leakage current increase. HSPICE simulation results show that junction leakage worsen SRAM cell stability by degrading SRAM read margin (SNM) and may eventually lead to cell failure.
Keywords :
SRAM chips; failure analysis; integrated circuit modelling; integrated circuit reliability; interface states; isolation technology; leakage currents; semiconductor junctions; technology CAD (electronics); BCT; Isolation test patterns; LPD transistor gate; PW misalignment; SRAM cell stability; SRAM degradation; SRAM junction reliability; SRAM read margin; STI interface traps; Si-SiO2; TCAD simulation; advance SRAM failure; butted contact; carrier transport; cell failure; electrical stress; isolation leakage current; junction leakage current; junction leakage mechanism; lower pull down transistor gate; off-state leakage current; photo misalignment; shallow trench isolation; trap-assisted carrier hopping; voltage dependence; weak temperature; Degradation; Junctions; Leakage currents; Random access memory; Reliability; Silicon; Stress; PW misalignment; isolation leakage current; junction leakage; read margin (SNM);
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Reliability Physics Symposium (IRPS), 2013 IEEE International
Conference_Location :
Anaheim, CA
ISSN :
1541-7026
Print_ISBN :
978-1-4799-0112-8
Electronic_ISBN :
1541-7026
Type :
conf
DOI :
10.1109/IRPS.2013.6531994
Filename :
6531994
Link To Document :
بازگشت