Title :
Circuit-dependent FMAX, Power and Process optimization to improve product Reliability, Availability and Serviceability
Author :
Nsame, P. ; Nadkarni, R. ; Klazynski, J.N. ; Bickford, Justin ; Sumner, K. ; Susso, B. ; Kumar, Ravindra ; Bazan, G. ; Polson, A. ; Radaker, R.
Author_Institution :
Syst. & Technol. Group, IBM Corp., Essex Junction, USA
Abstract :
A fully functional PowerPC476FP SoC communication processor with 4MB eDRAM System Cache achieving 2GHz/Core, in a 4 × 2.5DMIPS/Core/MHz configuration is qualified using physics-of-aging models in a 45nm SOI CMOS technology node including a logic and deep-trench (DT) eDRAM optimized semiconductor process. A novel circuit-depend F<;sub>MAX<;/sub>, Power, and Process optimization methodology that resolves technology reliability limitations (including Stress Migration, EM, BTI, HCI, TDDB, Defects, Package) without product burn-in, while delivering a 9.26% improvement per bin in energy-efficiency across 16 bins and up to 43.9% reduction in failure rate compare to equivalent circuits without the novel optimization methodology is described. Measured results show functional operation with a voltage range of 0.75V to 1.125V, a temperature range of -40C to 125C, speed of 1.8+ GHz at 0.96V, 110C and 90-100% yield performance, for a product lifetime specification of 88KPOH & 2750 ON/OFF cycles. These results demonstrate the highest reliability-aware functional performance reported to date with a 45nm nominal process at 0.9V for a 32-bit Quad-Core communication processor with asymmetric and scalable architecture while achieving the highest reported enterprise-level energy efficiency compare to Quad-Core communication processors in the same class. The technical contributions in this work enables a growing industry trend towards multi-radio ultra-compact stackable base stations designed to drastically reduce the entry price level per base station, enhance scalability and up-gradeability, significantly lower power consumption and enhance flexibility.
Keywords :
CMOS memory circuits; DRAM chips; cache storage; energy conservation; failure analysis; integrated circuit reliability; optimisation; silicon-on-insulator; system-on-chip; DT eDRAM optimized semiconductor process; SOI CMOS technology; circuit-dependent power; deep-trench eDRAM optimized semiconductor process; eDRAM system cache; enterprise-level energy efficiency; equivalent circuits; failure rate; frequency 1.8 GHz; frequency 2 GHz; fully functional PowerPC476FP SoC communication processor; logic eDRAM optimized semiconductor process; multiradio ultracompact stackable base stations; physics-of-aging models; power consumption; process optimization; product availability; product lifetime specification; product reliability; product serviceability; quadcore communication processor; reliability-aware functional performance; size 45 nm; storage capacity 32 bit; storage capacity 4 Mbit; technology reliability limitations; temperature -40 degC to 125 degC; voltage 0.75 V to 1.125 V; Availability; Error correction codes; Integrated circuit modeling; Integrated circuit reliability; Optimization; Reliability engineering;
Conference_Titel :
Reliability Physics Symposium (IRPS), 2013 IEEE International
Conference_Location :
Anaheim, CA
Print_ISBN :
978-1-4799-0112-8
Electronic_ISBN :
1541-7026
DOI :
10.1109/IRPS.2013.6531997