An array-based circuit for characterizing latent Plasma-Induced Damage

Author

Won Ho Choi ; Jain, Paril ; Kim, Chul Han

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of Minnesota, Minneapolis, MN, USA

fYear

2013

fDate

14-18 April 2013

Abstract

An array-based Plasma-Induced Damage (PID) characterization circuit with various antenna structures is proposed for efficient collection of massive PID breakdown statistics. The proposed circuit reduces the stress time and test area by a factor proportional to the number of Devices Under Test (DUTs). Measured Weibull statistics from a 12-24 array implemented in 65nm show that DUTs with plate type antennas have a shorter lifetime compared to their fork type counterparts suggesting greater PID effect during the plasma ashing process.

Keywords

VLSI; Weibull distribution; antenna arrays; electric breakdown; plasma devices; sputter etching; DUT; PID characterization circuit; PID effect; VLSI; Weibull statistics; antenna structures; array-based plasma-induced damage characterization circuit; devices under test; latent plasma-induced damage characterization; massive PID breakdown statistics; plasma ashing process; plate type antennas; size 65 nm; stress time; test area; time dependent dielectric breakdown; Antenna measurements; Antennas; Logic gates; Metals; Plasmas; Reliability; Stress; Aging; Plasma-induced damage; Time dependent dielectric breakdown; degradation;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium (IRPS), 2013 IEEE International

Conference_Location

Anaheim, CA

ISSN

1541-7026

Print_ISBN

978-1-4799-0112-8

Electronic_ISBN

1541-7026

Type

conf

DOI

10.1109/IRPS.2013.6532005

Filename

6532005