Impact of barrier integrity on liner reliability in 3D through silicon vias

For 3D chip stacking using Cu through silicon vias (TSV´s), dielectric liner reliability is crucial and is closely related to the barrier integrity. In this study, two different Cu barriers are compared in terms of dielectric liner reliability. By using two stress modes, where different voltage polarities are applied to the TSV, the impact of barrier integrity on liner reliability is segregated and PVD Ti is shown to be superior to PVD Ta for our particular liner. The field acceleration factors are extracted using classical TDDB and from controlled ramp rates, where a good match is found between the two methods. When applying a positive voltage to the TSV during stress, a bimodal distribution of the TDDB lifetime is observed for the PVD Ta barrier. This is linked to a competition between Cu induced dielectric breakdown and intrinsic dielectric breakdown.