Bias temperature instability and hot carrier circuit ageing simulations specificities in UTBB FDSOI 28nm node

Author

Angot, D. ; Huard, Vincent ; Federspiel, Xavier ; Cacho, F. ; Bravaix, A.

Author_Institution

STMicroelectron., Crolles, France

fYear

2013

fDate

14-18 April 2013

Abstract

We present new reliability features related to the use of a wide range of bulk back biasing in advanced UTBB FDSOI devices. NBTI and HCI stresses were done addressing degradation dependencies vs. bulk bias with the help of TCAD simulations in order to validate our new proposed NBTI physical model in UTBB FDSOI CMOS node.

Keywords

CMOS integrated circuits; circuit simulation; elemental semiconductors; integrated circuit design; integrated circuit modelling; integrated circuit reliability; silicon; silicon-on-insulator; stress analysis; technology CAD (electronics); thin film circuits; HCI stress; NBTI; Si; TCAD simulation; advanced UTBB FDSOI CMOS device node; bias temperature instability; bulk back biasing; hot carrier circuit ageing simulation; reliability; thin film device; ultrathin body and buried oxide; Degradation; Human computer interaction; Integrated circuit modeling; Integrated circuit reliability; Semiconductor device modeling; Stress; Bias Temperature damage; Hot-Carrier; TCAD simulations; UTBB FDSOI; ring oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium (IRPS), 2013 IEEE International

Conference_Location

Anaheim, CA

ISSN

1541-7026

Print_ISBN

978-1-4799-0112-8

Electronic_ISBN

1541-7026

Type

conf

DOI

10.1109/IRPS.2013.6532037

Filename

6532037