Title :
Tunnel transistors for energy efficient computing
Author :
Datta, Soupayan ; Bijesh, R. ; Liu, Hongying ; Mohata, D. ; Narayanan, Vijaykrishnan
Author_Institution :
Dept. of Electr. Eng., Pennsylvania State Univ., Univeristy Park, PA, USA
Abstract :
Tunnel transistor (TFET) is a potential steep slope device enabling supply voltage scaling. TFET is explored at the device and circuit level. Hetero-junction TFET is demonstrated with high drive current and high on-off current ratio. Hetero-junction TFETs with scaled device geometry can outperform Si FinFET at Vcc<;0.3V. Design considerations of TFET based circuits for logic and SRAM applications are investigated and performance benchmarked with Si FinFET technology.
Keywords :
tunnel transistors; SRAM applications; TFET based circuits; energy efficient computing; heterojunction TFET; high on-off current ratio; logic applications; silicon FinFET technology; steep slope device; supply voltage scaling; tunnel transistors; Adders; FinFETs; Gallium arsenide; Integrated circuit modeling; Logic gates; Silicon; Tunneling; III–V semiconductors; MBE TFET Verilog-A model; TFET SRAM design; TFET adder design; TFET circuit implementation; Tunnel FET; interface states; noise margin; steep slope; switching slope;
Conference_Titel :
Reliability Physics Symposium (IRPS), 2013 IEEE International
Conference_Location :
Anaheim, CA
Print_ISBN :
978-1-4799-0112-8
Electronic_ISBN :
1541-7026
DOI :
10.1109/IRPS.2013.6532046
