Ring oscillator reliability model to hardware correlation in 45nm SOI

Accurate CMOS reliability simulations are required at the circuit design stage in order to predict product lifetime. The physical mechanisms that cause transistor performance to degrade depend on operating conditions (temperature, bias), scale and technology of their design, as well as how the devices are topologically interconnected, loaded, and switched. This study investigates reliability model to hardware correlation of Cu 45nm Silicon-On-Insulator (SOI) ring oscillators, variations of which are altogether typical of digital logic paths. The contributions from physical degradation mechanisms of Negative Bias Temperature Instability (NBTI) and Hot-Carrier Injection (HCI) were modeled in RelXpert to produce degraded Spectre netlists. Simulations were found to be within acceptable accuracy for estimating aging induced performance changes in hardware, quantitatively compared in terms of the %-difference in the time-slope of the power regression of frequency degradation, as well as in the actual %-frequency degradation as a function of time. The main contribution of this work is in the accurate prediction of the extent of the dominant component degradation mechanisms in what may be the smallest scale thin-oxide devices that will ever be fabricated in production, reflecting that the NBTI and HCI mechanisms are well understood across scale variation approaching the atomic limit.