Suppression of bond degradation in power IC´s: Impact of bond pad design and wafer & package fab processes

The impact of bond-pad design, wafer fab and package fab process on bond degradation has been studied. Three groups of bond pad layer stacks with different pad metal area and current paths are compared. Top metal thickness, bond wire material, thickness of pad metal remaining under bond, and package type/molding material, are taken as process variables. It is found that pad designs where more metal levels are electrically involved perform significantly better. Which metal layer of the pad is connected to the circuit and how large the pad is are less important. Thicker pad metal helps to slow down the degradation. Bonds with Cu wire are of longer intrinsic Time-to-Fail (TTF) than Au wire. Times longer TTF is observed as the same test devices are packaged in a standard molded package instead of in an engineering package, indicating that package process can determine the bond degradation directly. The results are explained by electromigration (EM), intermetallic growth and interactions between pad design/wafer fab process with the package process. The insights will help to chosen better pad layout and process combinations regarding reliability, product design flexibility and cost reduction.