Title :
180nm FRAM reliability demonstration with ten years data retention at 125°C
Author :
Rodriguez, Jose ; Rodriguez-Latorre, J. ; Zhou, Changle ; Venugopal, A. ; Acosta, A. ; Ball, M. ; Ndai, P. ; Madan, S. ; McAdams, H. ; Udayakumar, K.R. ; Summerfelt, S. ; San, T. ; Moise, T.
Author_Institution :
Analog Technol. Dev., Texas Instrum. Inc. Dallas, Dallas, TX, USA
Abstract :
Reliability of a 2T-2C, 448kbit FRAM embedded within 180nm CMOS is presented. The results indicate a 10-year, 125°C data retention capability for this technology. Further, sufficient signal margin remains for sensing following 260°C Pb-free solder reflow step demonstrating that code data can be stored through the board-attach process. A new margin test approach, which enables depolarization effects to be quantified, has been developed. A model to estimate device fail rate based on array size, word length, error correction circuitry and bit error rate is also described.
Keywords :
CMOS memory circuits; error statistics; integrated circuit reliability; integrated circuit testing; random-access storage; reflow soldering; solders; 2T-2C; CMOS; FRAM reliability demonstration; Pb-free solder reflow; array size; bit error rate; board-attach process; code data; data retention capability; depolarization effect; device fail rate; error correction circuitry; margin test approach; signal margin; size 180 nm; temperature 125 C; temperature 260 C; word length; Arrays; Ferroelectric films; Nonvolatile memory; Random access memory; Reliability; Stress; Temperature measurement; 180nm analog CMOS; data cycling endurance; data retention; ferroelectric memory; non-volatile memory;
Conference_Titel :
Reliability Physics Symposium (IRPS), 2013 IEEE International
Conference_Location :
Anaheim, CA
Print_ISBN :
978-1-4799-0112-8
Electronic_ISBN :
1541-7026
DOI :
10.1109/IRPS.2013.6532102
