DocumentCode
608292
Title
A comprehensive soft error analysis tool for core networking system
Author
Haihong Zhu ; Wong, Rita ; ShiJie Wen
Author_Institution
Cisco Syst., San Jose, CA, USA
fYear
2013
fDate
14-18 April 2013
Abstract
In this paper, we developed a comprehensive single-event upset (SEU) analysis tool. To achieve this goal we start by defining the SEU mitigation strategy as a combination of chip level methods and system level methods. Given a particular SEU chip level and/or system level mitigation choice, we propose first categorizing the SEU Failure In Time (FIT) into different time window bins based on SEU recovery time. Then we analyze the impact of each mitigation strategy, results in the FIT value change in each bin. This tool enables the engineers to do the SEU mitigation design in early design phase. A user-friendly Excel format is also developed to make the complicated model easy to use. The system can be modeled using the tool at an early stage to support design decisions and trade-offs related to potentially costly mitigation strategies.
Keywords
integrated circuit design; integrated circuit reliability; radiation hardening (electronics); FIT; SEU analysis tool; SEU mitigation strategy; core networking system; failure in time; single-event upset; soft error analysis tool; user-friendly Excel format; Error analysis; Error correction codes; Field programmable gate arrays; Monitoring; Random access memory; Reliability; Single event upsets;
fLanguage
English
Publisher
ieee
Conference_Titel
Reliability Physics Symposium (IRPS), 2013 IEEE International
Conference_Location
Anaheim, CA
ISSN
1541-7026
Print_ISBN
978-1-4799-0112-8
Electronic_ISBN
1541-7026
Type
conf
DOI
10.1109/IRPS.2013.6532111
Filename
6532111
Link To Document