Title :
Estimation of hardened flip-flop neutron soft error rates using SRAM multiple-cell upset data in bulk CMOS
Author :
Gaspard, N. ; Jagannathan, Sarangapani ; Diggins, Z. ; McCurdy, M. ; Loveless, T.D. ; Bhuva, B.L. ; Massengill, Lloyd W. ; Holman, W.T. ; Oates, T.S. ; Fang, Y.-P. ; Wen, S.-J. ; Wong, Rita ; Lilja, K. ; Bounasser, M.
Author_Institution :
Dept. of Electr. Eng., Vanderbilt Univ., Nashville, TN, USA
Abstract :
Experimental neutron single-event error rates of 28-and 40-nm bulk CMOS hardened flip-flops are compared to various hardened flip-flop designs in literature. Using published 45-nm SRAM multiple-cell upset data, it is shown that the error rate of hardened flip-flop designs can be estimated by using the minimum sensitive node spacing from the flip-flop layout. Experimental data show that regardless of circuit topology of a hardened flip-flop, the redundant storage node spacing dominates neutron soft-error rates.
Keywords :
CMOS memory circuits; SRAM chips; flip-flops; neutron effects; radiation hardening (electronics); SRAM multiplecell upset data; bulk CMOS; hardened flip-flop neutron soft error rate; neutron single event error; size 28 nm; size 40 nm; size 45 nm; Flip-flops; Integrated circuits; Layout; Neutrons; Protons; Random access memory; Reliability; SRAM; hardened flip-flop; multiple-cell upset; neutron; single event; soft-error rate;
Conference_Titel :
Reliability Physics Symposium (IRPS), 2013 IEEE International
Conference_Location :
Anaheim, CA
Print_ISBN :
978-1-4799-0112-8
Electronic_ISBN :
1541-7026
DOI :
10.1109/IRPS.2013.6532113
