Effect of threshold voltage implants on single-event error rates of D flip-flops in 28-nm bulk CMOS

Author

Gaspard, N. ; Jagannathan, Sarangapani ; Diggins, Z. ; Kauppila, A.V. ; Loveless, T.D. ; Kauppila, J.S. ; Bhuva, B.L. ; Massengill, Lloyd W. ; Holman, W.T. ; Oates, Anthony S. ; Fang, Yi ; Wen, Shuli ; Wong, Rita

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Vanderbilt Univ., Nashville, TN, USA

fYear

2013

fDate

14-18 April 2013

Abstract

To understand the effects of threshold voltage implants on soft-error rate of a D flip-flop, three different designs were created using low, standard, and high voltage threshold implants in a 28-nm bulk technology. Experimental results show that the error rate is nearly the same for the three D flip-flop designs. This work attributes small critical charge and process variations across the flip-flop arrays as the main cause for similar soft-error rate of the flip-flops regardless of the threshold voltage implant.

Keywords

CMOS integrated circuits; flip-flops; radiation hardening (electronics); D flip-flops; bulk CMOS; single-event error rates; soft-error rate; threshold voltage implants; wavelength 28 nm; Error analysis; Flip-flops; Implants; Integrated circuits; Neutrons; Threshold voltage; Transistors; D flip-flop; heavy-ion; neutron; single event; soft-error rate; threshold voltage implant;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium (IRPS), 2013 IEEE International

Conference_Location

Anaheim, CA

ISSN

1541-7026

Print_ISBN

978-1-4799-0112-8

Electronic_ISBN

1541-7026

Type

conf

DOI

10.1109/IRPS.2013.6532114

Filename

6532114