Title :
Energy efficency of asynchronous and synchronous VLSI circuit on 40nm and 90nm FPGA
Author :
Pandey, Bishwajeet ; Yadav, J. ; Singh, Yatendra Kumar ; Swarnkar, Prashant
Author_Institution :
Atal Bihari Vajpayee (Indian Inst. of Inf. Technol. & Manage.), Gwalior, India
Abstract :
In this work, we analyze the power requirement of synchronous and asynchronous VLSI circuit. There is 70.42% overall power reduction using asynchronous arithmetic circuit in place of synchronous circuits. In asynchronous, FDCE is used whereas FDRSE is used in synchronous. On 90nm Spartan-3 target device, we are taking counter as target design and arithmetic circuit is target design on 40nm Virtex-6. Power consumption is different at any frequency using synchronous or asynchronous design on Virtex-6 but same on Spartan-3. There is 1.22%, 7.86%, 45.73%, 82.01%, 89.01%, 89.86% power reduction with reduction in frequency by a factor of 10 in range of 1MHz-1THz.
Keywords :
VLSI; asynchronous circuits; digital arithmetic; energy conservation; field programmable gate arrays; low-power electronics; power consumption; FDCE; FDRSE; FPGA; Spartan-3 target device; Virtex-6; asynchronous VLSI circuit; asynchronous arithmetic circuit; counter; energy efficiency; frequency 1 MHz to 1 THz; power consumption; size 40 nm; size 90 nm; synchronous VLSI circuit; Clocks; Conferences; Field programmable gate arrays; Frequency synchronization; Power demand; Radiation detectors; Synchronization; Asynchronous; Dynamic Power Reduction; Low Power Design; Synchronous;
Conference_Titel :
Energy Efficient Technologies for Sustainability (ICEETS), 2013 International Conference on
Conference_Location :
Nagercoil
Print_ISBN :
978-1-4673-6149-1
DOI :
10.1109/ICEETS.2013.6533357
