Analysis and solution to overcome EOS failure induced by latchup test in a high-voltage integrated circuits

Author

Hui-Wen Tsai ; Ming-Dou Ker ; Yi-Sheng Liu ; Ming-Nan Chuang

Author_Institution

Inst. of Electron., Nat. Chiao-Tung Univ., Hsinchu, Taiwan

fYear

2013

fDate

22-24 April 2013

Firstpage

1

Lastpage

4

Abstract

Proper layout and additional circuit solution have been proposed to solve the practical EOS failure induced by latchup test in an industry case of high-voltage integrated circuits (IC). The modified design has been implemented in 0.6-um 40-V BCD (Bipolar-CMOS-DMOS) process to successfully pass the 500-mA negative trigger current test. By eliminating overstress damages as happened in the prior work with only guard ring protection, the proposed solution can be adopted to implement high-voltage-applicable IC products which meet the requirement of industry applications with sufficient latchup immunity.

Keywords

BIMOS integrated circuits; failure analysis; integrated circuit layout; integrated circuit technology; integrated circuit testing; power integrated circuits; BCD process; EOS failure; current 500 mA; electrical overstress; guard ring protection; high-voltage integrated circuits; integrated circuit design; integrated circuit layout; latchup immunity; latchup test; negative trigger current test; overstress damage; size 0.6 mum; voltage 40 V; Current measurement; Earth Observing System; Integrated circuits; Layout; Regulators; Voltage control; Voltage measurement; Latchup; electrical overstress (EOS); high-voltage IC; regulator;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, Automation, and Test (VLSI-DAT), 2013 International Symposium on

Conference_Location

Hsinchu

Print_ISBN

978-1-4673-4435-7

Type

conf

DOI

10.1109/VLDI-DAT.2013.6533803

Filename

6533803