Title :
CMOS reliability: From discrete device degradation to circuit aging
Author_Institution :
GlobalFoundries, USA
Abstract :
Summary form only given. As we continue scaling towards 14 nm and beyond, reliability is becoming an integral part of the complete technology offering. Building in reliability is critical to the success of future scaling. As we marched towards the sub 100 nm technologies material changes have been necessary to meet the power, performance and reliability requirements. In sub 45 nm regime SiOx based dielectrics have been replaced by HK MG leading to new degradation mechanisms such as PBTI and also changed the understanding of existing mechanisms such as TDDB. As we scale further we need to comprehend interaction between device level variability pre and post stress and circuit functionality. In this talk I will address some of the challenges and correlation of device level reliability learning to simple circuits such ring oscillator and SRAM cells.
Keywords :
CMOS memory circuits; SRAM chips; ageing; integrated circuit reliability; oscillators; stress analysis; CMOS reliability; HK MG; PBTI; SRAM cell; SiOx based dielectrics; TDDB; circuit aging; device level variability; discrete device degradation mechanism; post stress functionality; pre-stress functionality; ring oscillator; size 100 nm; size 14 nm; size 45 nm; Aging; Buildings; CMOS integrated circuits; CMOS technology; Degradation; Integrated circuit reliability;
Conference_Titel :
VLSI Design, Automation, and Test (VLSI-DAT), 2013 International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4673-4435-7
DOI :
10.1109/VLDI-DAT.2013.6533830
