A low-power dual-mode continuous-time delta-sigma modulator with a folded quantizer

A dual-mode (2^nd/3^rd-order) continuous-time delta-sigma modulator with a proposed 4-bit folded quantizer is presented. The proposed folded quantizer achieves lower power consumption and saves quantizer hardware area. In addition, the dual-mode architecture provides the flexibility to satisfy the power consumption and resolution requirement. With a 1-MHz bandwidth and 64-MHz sampling rate, the measured peak SNDR and dynamic range for 2^nd/3^rd-order modulators are 55 dB/66 dB and 57 dB/68 dB, respectively. Fabricated in a 90-nm CMOS, the chip consumes 1.2 mW/1.5 mW from a 1.2-V supply voltage.