Time-domain analog-to-digital converters with domino delay lines

A time-domain analog-to-digital (ADC) based on a domino delay line for high-speed applications is presented. The structure is mainly built on digital blocks and is compatible with digital nanometer processes. The domino delay line consists of enhanced delay units and parallel reset for reducing the propagation delay. Dual-mode operation including a Nyquist mode and a sigma-delta modulation (SDM) mode can be provided by different processing of residue phases. Furthermore, a digital calibration technique is also proposed to compensate the inherently nonlinear behaviors. The proposed structure has been designed and implemented in a 0.18-μm standard CMOS process with active area of 0.01 mm². Same design is also ported and simulated in 90-nm, and 55-nm CMOS process, respectively. The figure-of-merit (FOM) of these ADCs can achieve 1.65, 0.28, and 0.07 pJ/Conversion-Step.