Title :
Time-domain analog-to-digital converters with domino delay lines
Author :
Chang-Ming Lai ; Yi-Chung Chen ; Po-Chiun Huang
Author_Institution :
Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Abstract :
A time-domain analog-to-digital (ADC) based on a domino delay line for high-speed applications is presented. The structure is mainly built on digital blocks and is compatible with digital nanometer processes. The domino delay line consists of enhanced delay units and parallel reset for reducing the propagation delay. Dual-mode operation including a Nyquist mode and a sigma-delta modulation (SDM) mode can be provided by different processing of residue phases. Furthermore, a digital calibration technique is also proposed to compensate the inherently nonlinear behaviors. The proposed structure has been designed and implemented in a 0.18-μm standard CMOS process with active area of 0.01 mm2. Same design is also ported and simulated in 90-nm, and 55-nm CMOS process, respectively. The figure-of-merit (FOM) of these ADCs can achieve 1.65, 0.28, and 0.07 pJ/Conversion-Step.
Keywords :
CMOS integrated circuits; calibration; sigma-delta modulation; ADC; CMOS; Nyquist mode; SDM mode; digital block; digital calibration technique; digital nanometer process; domino delay lines; dual-mode operation; high-speed application; nonlinear behavior compensation; parallel reset; propagation delay reduction; residue phase processing; sigma-delta modulation mode; size 55 nm; size 90 nm; time-domain analog-to-digital converter; CMOS process; Calibration; Delay lines; Delays; Propagation delay; Solid state circuits; Time-domain analysis; Analog-to-digital converters; domino delay line; time-domain analog-to-digital converters;
Conference_Titel :
VLSI Design, Automation, and Test (VLSI-DAT), 2013 International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4673-4435-7
DOI :
10.1109/VLDI-DAT.2013.6533841
