• DocumentCode
    609682
  • Title

    MVSE: A Multi-core Video decoder System level analytics Engine

  • Author

    Ding-Yun Chen ; Chi-Cheng Ju ; Chen-Tsai Ho ; Chung-Hung Tsai

  • Author_Institution
    Multimedia Dev. Div., Mediatek Inc., Hsinchu, Taiwan
  • fYear
    2013
  • fDate
    22-24 April 2013
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    Multi-core platform has become a trend in hand-held embedded systems, such as smartphone and tablet. To improve the video decoding performance by using the multiple cores, one of parallel algorithms should be adopted. However, different parallel algorithm should be selected for different video standard on different platform. Therefore, an engine to estimate performance on a target platform from existing single-thread video decoder is very helpful. This paper proposes a Multi-core Video decoder System level analytics Engine (MVSE) to estimate the performance on a target multi-core platform. In the MVSE, a general video decoder runs according to profiling data and macroblock information by three major parallel algorithms. The profiling data and macroblock information are obtained from existing single-thread video decoder so that the MVSE can support different video standard. The MVSE runs on target platform to consider the effect of memory access contention and cache intercommunication, which are traditionally difficult to estimate. Our experimental result shows the MVSE estimation is accuracy enough. The estimation results from MVSE shows the best speedup ratio is 1.7 times in a dual-core platform and 2.9 times in a quad-core platform for H.264 720p decoding. In addition, MVSE is also helpful for hardware and software co-design in heterogeneous computing. The experimental results show the best performance is improved by VLD hardware, and the speedup ratio is 2.3 times in a dual-core platform and 3.9 times in a quad-core platform.
  • Keywords
    data compression; hardware-software codesign; microprocessor chips; video coding; H.264 720p decoding; MVSE estimation; cache intercommunication; dual-core platform; hand-held embedded systems; hardware codesign; macroblock information; memory access contention; multicore video decoder system level analytics engine; multiple cores; parallel algorithms; quadcore platform; single-thread video decoder; software codesign; Decoding; Estimation; Hardware; Multicore processing; Parallel algorithms; Software; Streaming media;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, Automation, and Test (VLSI-DAT), 2013 International Symposium on
  • Conference_Location
    Hsinchu
  • Print_ISBN
    978-1-4673-4435-7
  • Type

    conf

  • DOI
    10.1109/VLDI-DAT.2013.6533859
  • Filename
    6533859