• DocumentCode
    609684
  • Title

    Case study of yield learning through in-house flow of volume diagnosis

  • Author

    Pei-Ying Hsueh ; Shuo-Fen Kuo ; Chao-Wen Tzeng ; Jih-Nung Lee ; Chi-Feng Wu

  • Author_Institution
    Realtek Semicond. Corp., Hsinchu, Taiwan
  • fYear
    2013
  • fDate
    22-24 April 2013
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    To find out the root causes of yield loss is always expensive and time-consuming. In this paper, we have developed an in-house flow of volume diagnosis. With the power of performing statistical analysis on the large volume of diagnosis results, we demonstrate that to do physical failure analysis could be in a more economical way. By utilizing the in-house flow of volume diagnosis, we could find out the defects which cause the yield loss primarily with only a few samples of failing dies in a single iteration. The industrial cases demonstrate the efficiency proved by the silicon data.
  • Keywords
    digital integrated circuits; elemental semiconductors; failure analysis; integrated circuit design; integrated circuit layout; silicon; statistical analysis; Si; economical way; in-house flow; industrial cases; physical failure analysis; single iteration; statistical analysis; volume diagnosis; yield learning; Failure analysis; Integrated circuits; Layout; Production; Silicon; Statistical analysis; Systematics; Layout-Aware Diagnosis; Volume Diagnosis; Yield Learning;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, Automation, and Test (VLSI-DAT), 2013 International Symposium on
  • Conference_Location
    Hsinchu
  • Print_ISBN
    978-1-4673-4435-7
  • Type

    conf

  • DOI
    10.1109/VLDI-DAT.2013.6533861
  • Filename
    6533861