A 0.5V/1.0V fast lock-in ADPLL for DVFS battery-powered devices

Author

Ching-Che Chung ; Duo Sheng ; Wei-Siang Su

Author_Institution

Dept. of Comput. Sci. & Inf. Eng., Nat. Chung Cheng Univ., Chiayi, Taiwan

fYear

2013

fDate

22-24 April 2013

Firstpage

1

Lastpage

4

Abstract

In this paper, a 0.5V/1.0V low-power all-digital phase-locked loop (ADPLL) for battery-powered devices with a dynamic voltage and frequency scaling (DVFS) scheme is presented. The proposed frequency estimation algorithm with a fine-resolution monotonic response digitally controlled oscillator (DCO), can quickly calculate the target control code for the DCO, and thus, the ADPLL can achieve a fast lock time in four clock cycles. The proposed ADPLL is implemented in a standard performance 65nm CMOS process with standard cells. The power consumption is 52.69μW at 600MHz with a 0.5V power supply and is 1.26mW at 1.28GHz with a 1.0V supply.

Keywords

CMOS digital integrated circuits; UHF oscillators; digital phase locked loops; frequency estimation; low-power electronics; CMOS process; DCO; DVFS battery-powered devices; clock cycles; dynamic voltage and frequency scaling scheme; fast lock-in ADPLL; fine-resolution monotonic response digitally controlled oscillator; frequency 1.28 GHz; frequency 600 MHz; frequency estimation algorithm; low-power all-digital phase-locked loop; power 1.26 mW; power 52.69 muW; size 65 nm; target control code; voltage 0.5 V; voltage 1.0 V; Clocks; Delays; Frequency control; Frequency conversion; Frequency estimation; Phase frequency detector; Phase locked loops;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, Automation, and Test (VLSI-DAT), 2013 International Symposium on

Conference_Location

Hsinchu

Print_ISBN

978-1-4673-4435-7

Type

conf

DOI

10.1109/VLDI-DAT.2013.6533868

Filename

6533868