A low-power delay-recycled all-digital duty-cycle corrector with unbalanced process variations tolerance

In this paper, a low-power delay-recycled all-digital duty-cycle corrector (ADDCC) is presented. The proposed ADDCC corrects the duty-cycle of the distorted clock to 50% under process, voltage, and temperature (PVT) variations. Besides, the delay-recycled architecture reduces the required length of the delay line to 1/2 of the input clock period. The proposed ADDCC architecture saves both the chip area and the power consumption. In addition, the proposed ADDCC can work properly at unbalanced process corners (i.e. SF and FS). The proposed design is implemented in a standard performance 90nm CMOS process, and the active area is 70 μm × 70 μm. The simulation results show that the maximum duty cycle error of the output clock can be less than 1.9% with the input duty-cycle ranging from 20% to 80 %, and the input frequency ranging from 450 MHz to 1 GHz. The power consumption of the proposed ADDCC is 1.7mW at 450MHz and 3.45mW at 1 GHz with a 1.0V power supply.