A low-power design methodology for sigma-delta modulators with relaxation of required circuit specifications

A design methodology of high-order sigma-delta modulators (SDMs) with relaxation of required circuit specifications is proposed to reduce the required power consumption and to be suitable for the nano-scale circuit. According to the proposed design flow, more relaxed circuit specifications can be selected so that designers can maintain system performance. One design example is employed to verify the proposed design flow. Circuit-level simulation reveals that the power consumption is lower under the same system performance compared with a conventional design flow. The circuits are implement with TSMC 90nm 1P9M CMOS process and the measured signal-to-noise distortion ratio (SNDR) is 64.5 dB, with a power consumption of 303μW.