Analysis of the leakage effect in a pipelined ADC with nanoscale CMOS technologies

Author

Chin-Yu Lin ; Yen-Chuan Huang ; Tai-Cheng Lee

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

fYear

2013

fDate

22-24 April 2013

Firstpage

1

Lastpage

4

Abstract

The thin oxide and short channel of the MOS transistor induce significant leakage currents in nanoscale CMOS technologies. In this paper, the effect arisen from the leakage currents, including gate direct-tunneling and subthreshold conduction, are discussed in a sample-and-hold (S/H) circuit. A model of the worst leakage error is proposed based on a small-signal circuit model. Based on the proposed leakage model, an 8-bit 100-MS/s pipelined ADC was designed in a general purpose 90-nm CMOS technology. The measured SNDR is 45 dB and the power consumption is 24 mW running from a 1.0-V supply.

Keywords

CMOS integrated circuits; analogue-digital conversion; integrated circuit design; leakage currents; sample and hold circuits; tunnelling; S-H; gate direct-tunneling; leakage effect analysis; nanoscale CMOS technology; noise figure 45 dB; pipelined ADC; power 24 mW; power consumption; sample-and-hold circuit; short channel MOS transistor; size 90 nm; small-signal circuit model; subthreshold conduction; thin oxide MOS transistor; voltage 1.0 V; word length 8 bit; CMOS integrated circuits; CMOS technology; Leakage currents; Logic gates; MOSFET; Subthreshold current; Tunneling; gate tunneling leakage; pipelined ADC; sample-and-hold (S/H); subthreshold conduction;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, Automation, and Test (VLSI-DAT), 2013 International Symposium on

Conference_Location

Hsinchu

Print_ISBN

978-1-4673-4435-7

Type

conf

DOI

10.1109/VLDI-DAT.2013.6533874

Filename

6533874