Enabling inter-die co-optimization in 3-D IC with TSVs

Even though three-dimensional integrated circuits (3-D ICs) with through silicon vias (TSVs) potentially provide modern electronic devices with various advantages, current commercial tools do not realize their layout as a whole, but one by one in a stack of dies. The capability of inter-die co-optimization remains largely restricted. This is, in part, due to that the tools draw heavily on 2-D IC´s design and implementation styles. Inter-die co-optimization is imperative for 3-D ICs where timing, power, and area are simultaneously considered. In this paper, we show how to enable inter-die co-optimization with adaptive buffering. Empirical results indicate that the proposed scheme eliminates iterative routines, which can help hasten the pace of realizing 3-D integration.