DocumentCode
609709
Title
On the futility of thermal through-silicon-vias
Author
Chung-Han Chou ; Nien-Yu Tsai ; Hao Yu ; Yiyu Shi ; Jui-Hung Chien ; Shih-Chieh Chang
Author_Institution
Comput. Sci. Dept., Nat. Tsing Hua Univ., Hsinchu, Taiwan
fYear
2013
fDate
22-24 April 2013
Firstpage
1
Lastpage
6
Abstract
Thermal integrity is one of the most important challenges faced by three-dimensional integrated circuits (3D ICs). Towards this, thermal through-silicon-vias (TTSVs) have been widely used to assist heat dissipation. The metal inside TTSVs can conduct heat more effectively than the silicon substrate, and the metal bumps underneath TTSVs can help heat penetrate through the inter-layer thermal interface material (TIM). However, the surrounding silicon dioxide blocks the heat flowing into them. This makes the effectiveness of TTSVs questionable. In this paper, we argue that some existing TTSV models fail to capture those effects. Experimental results based on finite element simulations verify and confirm that the temperature reduction is indeed brought by the metal bumps underneath the TTSVs rather than the TTSVs themselves. We demonstrate that it is sufficient to add bumps between tiers to reduce temperature without wasting silicon area.
Keywords
cooling; integrated circuit packaging; thermal management (packaging); three-dimensional integrated circuits; 3D IC; TIM; TTSV; heat dissipation; metal bumps; silicon area; silicon dioxide; silicon substrate; temperature reduction; thermal interface material; thermal through-silicon-vias; three-dimensional integrated circuits; Conductivity; Heating; Metals; Stacking; Substrates; Thermal conductivity; Through-silicon vias;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, Automation, and Test (VLSI-DAT), 2013 International Symposium on
Conference_Location
Hsinchu
Print_ISBN
978-1-4673-4435-7
Type
conf
DOI
10.1109/VLDI-DAT.2013.6533886
Filename
6533886
Link To Document