Numerical simulation and experimental verification of copper plating with different additives for through silicon vias

The Filling of high aspect ratio through silicon vias (TSVs) using copper plating without any void or seam is one of the technical challenges for 3D integration. This paper presents numerical simulation and experimental verification of copper plating with different additives and a guideline for process optimization is proposed. Theoretical models are derived and a generic calculating approach is developed by employing a variable boundary method using commercial software. The simulation results can predict the behaviors of copper plating with different levels of additives for blind vias. The further experimental results verified the theoretical model and the simulation results. TSVs with diameter of 30μm and depth of 160μm on 8 inch wafers without void or seam have been achieved.