Study on Insert-Bump bonding process for multi-chip package

3D packaging technologies using TSV (Through-Silicon Via) has been studied widely in the recent years to achieve higher packaging density, lower power consumption and higher electrical performance because electrical line is shorter and Cu TSV has smaller electrical resistivity than any other package. However, there are many technical issues such as thin wafer/chip handling, TSV electrical and mechanical reliability due to Cu metal, inspection and bonding process for multi-stacking to commercialize this package. Especially, bonding process is key technology to increase yield. To stack chips vertically, reliable and robust bonding technique is required because multi-stacking chips causes misalignment between chips during bonding process and thermal stress is induced by thermal cycle. Cu pillar bump bonding process is usually used to interconnect chips vertically although backside and front-side bumping process is needed and also has weak shape to mechanical stress such as thermal stress. In this work, we suggested Insert-Bump bonding (ISB) process newly to stack multi-layer chips successively. ISB bonding process could simplify bonding process compared to Cu pillar bonding because it uses recessed Cu nail bump, which is formed by RIE process of back-side opened TSV and Planar Sn/3Ag pool-planar bump, which is fabricated by CMP(Chemical-Mechanical Polishing) process of electroplated Sn-3Ag layer without lithography to pattern bumps. Through experiments, we tried to find optimal bonding conditions such as bonding temperature and bonding pressure and also evaluated fluxing and no-fluxing cases. Although no-fluxing bonding process was applied to ISB bonding process, we could accomplish good bonding interface at 250°C due to oxide layer breakage effects.