Design and implementation of OFDMA-based WLAN prototype system

This paper presents design and implementation results of an OFDMA-based Wireless LAN (WLAN) prototype system using FPGA technology and Verilog HDL hardware description language. The whole hardware platform is composed of base band processor, Digital-to-Analog Converter (DAC)/Analog To Digital Converter (ADC) adapter board and RF front end. The hardware modules of the OFDMA transceiver presented in this paper include training sequences, pilot inserting, Cyclic Prefix (CP) adding, IFFT/FFT, synchronization, and channel equalization. The final implementation consists of two identical Virtex-5 FPGA development boards, offering dual channel high performance ADCs and DACs, required for operation in the licensed ITS band of 5.8GHz. The system is used to test and verify Next Ultra High Throughput WLAN (NUHT) 1.0 PHY standard.