DocumentCode :
610099
Title :
Differential Base Pattern Coding for Cache Line Data Compression
Author :
Kaneko, Hironori ; Fujii, Shohei ; Sasaki, Hiromu
Author_Institution :
Tokyo Inst. of Technol., Tokyo, Japan
fYear :
2013
fDate :
20-22 March 2013
Firstpage :
499
Lastpage :
499
Abstract :
The computational performance of recent processors is often restricted by the delay of off-chip memory accesses, and so low-delay data compression should be effective to improve the processor performance. This paper proposes differential base pattern coding suitable for high-speed parallel decoding. Evaluation shows that the compression ratio of the coding is comparable or superior to that of conventional codings.
Keywords :
cache storage; data compression; decoding; cache line data compression; coding compression ratio; differential base pattern coding; high-speed parallel decoding; low-delay data compression; off-chip memory access; processor computational performance; Abstracts; Data compression; Delays; Encoding; Graphics processing units; Vectors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Data Compression Conference (DCC), 2013
Conference_Location :
Snowbird, UT
ISSN :
1068-0314
Print_ISBN :
978-1-4673-6037-1
Type :
conf
DOI :
10.1109/DCC.2013.79
Filename :
6543109
Link To Document :
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