Title :
On the potential of CRS, 1D1R, and 1S1R crossbar RRAM for storage-class memory
Author :
Chun-Li Lo ; Mei-Chin Chen ; Jiun-Jia Huang ; Tuo-Hung Hou
Author_Institution :
Dept. of Electron. Eng. & Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
An All-LPU scheme with improved read margin is the most favorable for parallel read. RL is the predominant factor of read margin for array size beyond Mb regardless of CRS, 1D1R, or 1S1R, but sufficient read margin is expected for a 16-Mb array. However, unreliable write is the major obstacle in CRS and 1D1R. The 1S1R crossbar RRAM with excellent read and write margins using high-bandwidth parallel schemes has the most potential as a new-generation SCM.
Keywords :
random-access storage; rewriting systems; 1D1R; 1S1R crossbar RRAM; CRS; all-LPU scheme; array size; high-bandwidth parallel schemes; new-generation SCM; parallel read; predominant factor; read and write margins; read margin; storage-class memory; unreliable write; Arrays; Bandwidth; Electron devices; Hafnium oxide; Nickel; Resistance; Switches;
Conference_Titel :
VLSI Technology, Systems, and Applications (VLSI-TSA), 2013 International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4673-3081-7
Electronic_ISBN :
978-1-4673-6422-5
DOI :
10.1109/VLSI-TSA.2013.6545588
