Self-align nitride based logic NVM in 28nm high-k metal gate CMOS technology

Author

Lin, P.Y. ; Yang, T.H. ; Sung, Y.T. ; Lin, C.J. ; King, Y.C. ; Chang, T.S.

Author_Institution

Microelectron. Lab., Nat. Tsing-Hua Univ., Hsinchu, Taiwan

fYear

2013

fDate

22-24 April 2013

Firstpage

1

Lastpage

2

Abstract

Self-align nitride (SAN) logic NVM cell has been successfully demonstrated in 28nm CMOS technology with high-k gate dielectric layer and metal gate WL for coupling. This work proposed a new method for program and erase of the SAN cells, when gate length and gate spacing scales aggressively to 40nm and 70nm, respectively. Reliable 2-bit per cell operation by local hot hole injection controlled by metal gate WLs are demonstrated successfully for future applications of high density logic NVM arrays.

Keywords

CMOS integrated circuits; dielectric materials; logic arrays; random-access storage; SAN cell; gate length; gate spacing scale; high density logic NVM array; high-k gate dielectric layer; high-k metal gate CMOS technology; hot hole injection; metal gate WL; self-align nitride; size 28 nm; CMOS integrated circuits; Dielectrics; High K dielectric materials; Logic gates; Metals; Nonvolatile memory; Storage area networks;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems, and Applications (VLSI-TSA), 2013 International Symposium on

Conference_Location

Hsinchu

Print_ISBN

978-1-4673-3081-7

Electronic_ISBN

978-1-4673-6422-5

Type

conf

DOI

10.1109/VLSI-TSA.2013.6545594

Filename

6545594