Comprehensive study for RF interference limited 3D TSV optimization

RF interference in Through-Silicon-Via (TSV) 3D chip stacking technology was studied using device parameters from ITRS roadmap. Several new design parameters were defined and optimized based on the calculation. First, chip-to-chip RF interference using TSVs with μ-bump and solder was studied. It was found that the interference was primarily affected by TSV pitch and frequency through the capacitive coupling with Si substrate. For more realistic condition with integration processes, we studied the interference in terms of TSV misalignment and multi-chip stacking. The misaligned TSV stacks increased the interference (S13) and it becomes 0.6dB of increment when the misalignment was 25μm. In case of multi-chip stacking, RF interference between TSVs increases 20dB when 5 layers stacked. Based on the various stacking scenarios of 3D TSV, design guidelines of TSV integration process and design are suggested to minimize the RF interference.