DocumentCode
610611
Title
Opportunities and challenges of 3D NAND scaling
Author
Goda, Akira
Author_Institution
Micron Technol., Boise, ID, USA
fYear
2013
fDate
22-24 April 2013
Firstpage
1
Lastpage
2
Abstract
3D NAND is attracting increasing attention as a NAND scaling solution. In 3D NAND, the physical cell size is decoupled from the effective cell size by stacking multiple tiers. This enables effective NAND cell size scaling without degrading cell performance and reliability. However, 3D process integration could introduce new sources of cell degradation. This paper will discuss the opportunities and challenges of 3D NAND scaling.
Keywords
NAND circuits; integrated logic circuits; three-dimensional integrated circuits; 3D NAND scaling; effective cell size; physical cell size; Computer architecture; Degradation; Logic gates; Microprocessors; Programming; Three-dimensional displays; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, Systems, and Applications (VLSI-TSA), 2013 International Symposium on
Conference_Location
Hsinchu
Print_ISBN
978-1-4673-3081-7
Electronic_ISBN
978-1-4673-6422-5
Type
conf
DOI
10.1109/VLSI-TSA.2013.6545625
Filename
6545625
Link To Document