Bit Cost Scalable (BiCS) technology for future ultra high density memories

Author

Nitayama, A. ; Aochi, H.

Author_Institution

Center for Semicond. R&D, Toshiba Corp., Yokkaichi, Japan

fYear

2013

fDate

22-24 April 2013

Firstpage

1

Lastpage

2

Abstract

We proposed Bit Cost Scalable (BiCS) technology in 2007 as a three-dimensional memory for the future ultra high density storage devices, which extremely reduce the bit costs by vertically stacking memory arrays with punch and plug process. We´ve applied it to just NAND flash, which is BiCS Flash memory, and established the mass production technology. Moreover, we can apply the BiCS technology to various memories. The critical issues and the comparison among various 3D NAND Flash-type memories are to be discussed, as well.

Keywords

NAND circuits; flash memories; mass production; 3D NAND flash-type memories; BiCS flash memory; BiCS technology; bit cost scalable; mass production; memory arrays; plug process; punch process; three-dimensional memory; ultrahigh density memories; ultrahigh density storage devices; Electrodes; Films; Flash memories; Logic gates; SONOS devices; Three-dimensional displays; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems, and Applications (VLSI-TSA), 2013 International Symposium on

Conference_Location

Hsinchu

Print_ISBN

978-1-4673-3081-7

Electronic_ISBN

978-1-4673-6422-5

Type

conf

DOI

10.1109/VLSI-TSA.2013.6545626

Filename

6545626