SoC level considerations of 3D technology architecture

This paper summarizes circuit and 3D device interactions on System-on-Chip (SoC) architectures. The electrostatics of 3D devices is shown to depend on fin structural parameters such as fin width, height and taper. The nature of the current flow in 3D devices, careful design of Source/Drain region volume, contact shape and proximity to channel are critical to achieve optimum device performance. Key device structural features, their impact on electrostatics and drive current along with critical pitches and their impact on SoC level metrics are discussed.