Junction engineering for FDSOI technology speed/power enhancement

Author

Weber, Olivier ; Planes, N. ; Barral, V. ; Barge, D. ; Richard, Evelyne ; Dumont, Benjamin ; Perreau, P. ; Petit, D. ; Golanski, Dominique ; Fenouillet-Beranger, C. ; Guillot, N. ; Lagrasta, S. ; Gouraud, P. ; Campidelli, Y. ; Pinzelli, L. ; Mellier, M. ;

Author_Institution

STMicroelectron., Crolles, France

fYear

2013

fDate

22-24 April 2013

Firstpage

1

Lastpage

2

Abstract

This work highlights the way to optimize the speed/power performance of the planar FDSOI technology at the 28nm node and beyond. The combination of gate length shrink and spacerO increase leads to 13% delay decrease and 15% dynamic power saving at same speed through capacitance reduction. It demonstrates that, as far as the access resistance penalty is kept reasonably low, increasing the spacerO is highly efficient to boost AC performance in FDSOI.

Keywords

MOSFET; capacitance; electric resistance; semiconductor junctions; silicon-on-insulator; AC performance; access resistance penalty; capacitance reduction; dynamic power saving; gate length shrink; junction engineering; planar FDSOI technology; size 28 nm; spacerO; speed/power performance;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems, and Applications (VLSI-TSA), 2013 International Symposium on

Conference_Location

Hsinchu

Print_ISBN

978-1-4673-3081-7

Electronic_ISBN

978-1-4673-6422-5

Type

conf

DOI

10.1109/VLSI-TSA.2013.6545645

Filename

6545645