Timing variation aware dynamic digital phase detector for low-latency clock domain crossing

This study presents a digital phase detector-based approach for estimating and synchronising phase variations between clock domains. Instead of waiting for the resolution of metastability (with finite probability of failure), the authors propose a metastability avoidance algorithm, based on a sampling method for asynchronous signals. The results, using 90 nm inovation for high performance microelectronics (IHP) technology, show that the proposed design is about 1.5 times faster and provides a 35% improvement in Energy-Delay Product compared with the state-of-the-art approaches. Moreover, it completely prevents metastability failures.