• DocumentCode
    610855
  • Title

    A Fast Circuit Topology for Finding the Maximum of N k-bit Numbers

  • Author

    Yuce, Bilgiday ; Ugurdag, H. Fatih ; Goren, Sezer ; Dundar, Gunhan

  • Author_Institution
    Bogazici Univ., Istanbul, Turkey
  • fYear
    2013
  • fDate
    7-10 April 2013
  • Firstpage
    59
  • Lastpage
    66
  • Abstract
    Finding the value and/or address (position) of the maximum element of a set of binary numbers is a fundamental arithmetic operation. Numerous systems, which are used in different application areas, require fast (low-latency) circuits to carry out this operation. We propose a fast circuit topology called Array-Based maximum finder (AB) to determine both value and address of the maximum element within an n-element set of k-bit binary numbers. AB is based on carrying out all of the required comparisons in parallel and then simultaneously computing the address as well as the value of the maximum element. This approach ends up with only one comparator on the critical path, followed by some selection logic. The time complexity of the proposed architecture is O(log2n + log2k) whereas the area complexity is O(n2k). We developed RTL code generators for AB as well as its competitors. These generators are scalable to any value of n and k. We applied a standard-cell based iterative synthesis flow that finds the optimum time constraint through binary search. The synthesis results showed that AB is 1.2-2.1 times (1.6 times on the average) faster than the state-of-the-art.
  • Keywords
    computational complexity; digital arithmetic; iterative methods; network topology; program compilers; AB; RTL code generators; area complexity; arithmetic operation; array-based maximum finder; binary search; fast circuit topology; k-bit binary numbers; standard-cell based iterative synthesis flow; time complexity; Arrays; Binary trees; Circuit topology; Delays; Logic gates; Time complexity; Topology; Area-timing product; Computer arithmetic; Logic synthesis; Maximum finder; Minimum finder; Timing optimization;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Arithmetic (ARITH), 2013 21st IEEE Symposium on
  • Conference_Location
    Austin, TX
  • ISSN
    1063-6889
  • Print_ISBN
    978-1-4673-5644-2
  • Type

    conf

  • DOI
    10.1109/ARITH.2013.35
  • Filename
    6545892