ShrinkWrap: Compiler-Enabled Optimization and Customization of Soft Memory Interconnects

Author

Chung, Eric S. ; Papamichael, Michael K.

fYear

2013

fDate

28-30 April 2013

Firstpage

113

Lastpage

116

Abstract

Today´s FPGAs lack dedicated on-chip memory interconnects, requiring users to (1) rely on inefficient, general-purpose solutions, or (2) tediously create an application-specific memory interconnect for each target platform. The CoRAM architecture, which offers a general-purpose abstraction for FPGA memory management, encodes high-level application information that can be exploited to generate customized soft memory interconnects. This paper describes the ShrinkWrap Compiler, which analyzes a CoRAM application for its connectivity and bandwidth requirements, enabling synthesis of highly-tuned area-efficient soft memory interconnects.

Keywords

SRAM chips; field programmable gate arrays; integrated circuit design; memory architecture; program compilers; storage management chips; CoRAM architecture; FPGA memory management; SRAM; ShrinkWrap; bandwidth requirements; compiler-enabled customization; compiler-enabled optimization; connectivity requirements; general-purpose abstraction; high-level application information; on-chip memory interconnects; soft memory interconnects; Bandwidth; Field programmable gate arrays; Instruction sets; Memory management; Optimization; Random access memory; Throughput; accelerator; fpga; network-on-chip; system-on-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

Field-Programmable Custom Computing Machines (FCCM), 2013 IEEE 21st Annual International Symposium on

Conference_Location

Seattle, WA

Print_ISBN

978-1-4673-6005-0

Type

conf

DOI

10.1109/FCCM.2013.56

Filename

6546004