• DocumentCode
    611119
  • Title

    Modular Redundancy in a GALS System Using Asynchronous Recovery Links

  • Author

    Lechner, Jakob ; Veeravalli, Varadan S.

  • Author_Institution
    Inst. of Comput. Eng., Vienna Univ. of Technol., Vienna, Austria
  • fYear
    2013
  • fDate
    19-22 May 2013
  • Firstpage
    23
  • Lastpage
    30
  • Abstract
    In this paper we describe a new design approach for fault-tolerant globally asynchronous locally synchronous (GALS) systems using triple modular redundancy. The paper proposes a recovery and voting mechanism that relies on asynchronous, delay-insensitive links for state exchange. Thereby the replicated module copies remain fully timing-independent and only need to be locally synchronized. This allows for extremely flexible module partitioning and placement: Triplicated modules could be arranged on a single die, or be mapped to three separate chips to minimize the risk of two copies failing at the same time. In the first part of the paper we discuss the general concept of the recovery mechanism and the requirements for the design of the GALS modules to ensure replica determinism. The second part of the paper then presents the implementation of a lightweight recovery controller, which consists of both synchronous and asynchronous components. To access the internal state of a module we re-use the scan chains, which are typically included in every synchronous circuit for testing purposes. The robustness of our solution is verified by exhaustive fault-injection experiments.
  • Keywords
    asynchronous circuits; fault tolerance; redundancy; GALS system; asynchronous components; asynchronous delay-insensitive links; asynchronous recovery-voting mechanism; exhaustive fault-injection experiments; fault-tolerant globally asynchronous locally synchronous system; flexible module partitioning; lightweight recovery controller; replica determinism; scan chains; synchronous circuit; synchronous components; triple modular redundancy; Asynchronous circuits; Delay-insensitivity; Fault-tolerance; GALS; Recovery; Scan chain; TMR;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Asynchronous Circuits and Systems (ASYNC), 2013 IEEE 19th International Symposium on
  • Conference_Location
    Santa Monica, CA
  • ISSN
    1522-8681
  • Print_ISBN
    978-1-4673-5956-6
  • Type

    conf

  • DOI
    10.1109/ASYNC.2013.23
  • Filename
    6546174