DocumentCode :
611120
Title :
An SET Tolerant Tree Arbiter Cell
Author :
Naqvi, S.R. ; Steininger, Andreas ; Lechner, Jakob
Author_Institution :
Vienna Univ. of Technol., Vienna, Austria
fYear :
2013
fDate :
19-22 May 2013
Firstpage :
31
Lastpage :
39
Abstract :
Due to their inherently in deterministic behavior arbiters cannot simply be made fault tolerant by replication. We present an in-depth analysis of a tree arbiter cell with respect to possible faults and failure modes. Based on these results we devise a fault tolerant implementation of this cell that carefully avoids all single points of failure and can hence withstand transient faults as well as bit flips in its stateful elements. We verify the fault tolerance of our implementation by means of model checking and compare its overheads and performance penalties with a TMR-based solution. While the validation confirms that our approach is indeed suitable for use within an overall fault tolerance concept, the penalties turn out to be lower than for a comparable TMR approach.
Keywords :
VLSI; failure analysis; fault tolerance; formal verification; trees (mathematics); tunnelling magnetoresistance; SET tolerant tree arbiter cell; TMR-based solution; failure modes; in-depth analysis; indeterministic behavior arbiters; model checking; single failure points; transient faults;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Asynchronous Circuits and Systems (ASYNC), 2013 IEEE 19th International Symposium on
Conference_Location :
Santa Monica, CA
ISSN :
1522-8681
Print_ISBN :
978-1-4673-5956-6
Type :
conf
DOI :
10.1109/ASYNC.2013.22
Filename :
6546175
Link To Document :
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