GALS Design for Spectral Peak Attenuation of Switching Current

Digital circuits often suffer from the switching noise when synchronized by a global clock. This work investigates the spectral peak attenuation of the switching current by applying Globally Asynchronous Locally Synchronous (GALS) design. It is theoretically proven that, in particular for a plesiochronous design with M clock domains, an attenuation of up to 20logM dB can be achieved at lower order harmonics of the clock frequency. Power-consumption balanced GALS partitioning is found to be preferred for spectral noise attenuation, since it provides robustness against the current shape variations in individual blocks. Experiments on a 130-nm CMOS synchronous/GALS dual-core FMCW-RADAR chip, named Lighthouse, have been performed. Comparing with the synchronous design, on the on-chip power supply, a spectral peak attenuation of 12.29 dB at the fundamental clock frequency can be measured for the power balanced GALS design with five plesio-chronous clocks.