A Bit of Analysis on Self-Timed Single-Bit On-Chip Links

We present a study of five different self-timed single-bit on-chip links implemented in 90 nm, 65 nm, and 45 nm process technologies. These include representative examples of Quasi Delay-Insensitive, single-track, ternary, and voltage-scaled links, as well as a link of our own design intended to minimize wire usage. We characterize the tradeoffs between throughput, energy, and area for planar wiring as well as 3D through-silicon vias. We also describe our multi-objective optimization framework for exploring this parameter space.