DocumentCode :
61161
Title :
A Core Compact Model for Multiple-Gate Junctionless FETs
Author :
Jae Hur ; Dong-Il Moon ; Ji-Min Choi ; Myeong-Lok Seol ; Ui-Sik Jeong ; Chang-Hoon Jeon ; Yang-Kyu Choi
Author_Institution :
Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea
Volume :
62
Issue :
7
fYear :
2015
fDate :
Jul-15
Firstpage :
2285
Lastpage :
2291
Abstract :
A core model for multiple-gate junctionless FETs (Mug-JL-FETs) is proposed. The derived charge model is obtained via assumptions of simple potential profile for different types of Mug-JL-FETs. It was found that the linear potential approach is not accurate enough for a double-gate (DG) JL-FET, whereas it was reasonably precise for a DG inversion-mode FET. This discrepancy arises from their different operating mechanisms. Thus, the parabolic potential assumption, which is intuitively close to an actual potential profile in the Mug-FETs, was applied. As a consequence, two different formulas of the charge model in terms of depletion charges, gate capacitance, and capacitance inside the channel were found: one for a tetragonal shape of a cross-sectional channel based on a Cartesian coordinate and the other for a circular shape of a cross-sectional channel based on a cylindrical coordinate. Moreover, the proposed approach was applied for a realistically shaped channel, which is close to elliptic geometry, with a circular profile at the top and bottom parts of the channel and a rectangular profile at the center part of the channel. By applying the decoupling method reported previously, a drain current model, which is extended from the above-mentioned charge model, was also obtained.
Keywords :
field effect transistors; Cartesian coordinate; DG inversion mode FET; Mug-JL-FET; charge model; circular profile; circular shape; core compact model; cross-sectional channel; cylindrical coordinate; decoupling method; depletion charge; double-gate JL-FET; drain current model; elliptic geometry; gate capacitance; linear potential approach; multiple-gate junctionless FET; parabolic potential assumption; potential profile; rectangular profile; tetragonal shape; Capacitance; Electric potential; Field effect transistors; Logic gates; Mathematical model; Mobile communication; Numerical models; Core model; cylindrical gate-all-around (Cy-GAA) FET; double-gate (DG) FET; junctionless FET (JL-FET); multiple gate; rectangular gate-all-around FET (Re-GAA-FET); triple-gate FET (TG-FET); triple-gate FET (TG-FET).;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/TED.2015.2428711
Filename :
7105899
Link To Document :
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