FPGA implementation of retimed low power and high throughput DCT core using NEDA

Author

Mankar, A. ; Prasad, Narayan ; Das, A.D.

Author_Institution

Dept. of Electron. & Commun. Eng., Nat. Inst. of Technol., Rourkela, India

fYear

2013

fDate

12-14 April 2013

Firstpage

1

Lastpage

4

Abstract

Discrete Cosine Transform (DCT) is a popular technique used for converting signal into elementary frequency components. NEw Distributed Arithmetic (NEDA) is an efficient method for implementing inner products without using multipliers and ROM. In this present design, we have proposed the implementation of 1D DCT using NEDA, considering retiming technique. The outputs are obtained at every clock cycle. The maximum frequency obtained is 311.943 MHz and the throughput is of 3431.384 Mbit/s. The slice delay product of the proposed design is 1.734. The proposed design consumes 2.76 W at its maximum frequency.

Keywords

digital arithmetic; discrete cosine transforms; field programmable gate arrays; multiplying circuits; read-only storage; FPGA implementation; NEDA; ROM; bit rate 3431.384 Mbit/s; discrete cosine transform; elementary frequency component; high throughput DCT core; multiplier; new distributed arithmetic; power 2.76 W; retimed low power; retiming technique; signal conversion; Computer architecture; Discrete cosine transforms; Equations; Field programmable gate arrays; Mathematical model; Read only memory; Throughput; DCT; FPGA; NEDA; low power; retiming;

fLanguage

English

Publisher

ieee

Conference_Titel

Engineering and Systems (SCES), 2013 Students Conference on

Conference_Location

Allahabad

Print_ISBN

978-1-4673-5628-2

Type

conf

DOI

10.1109/SCES.2013.6547521

Filename

6547521