High performance Multi Threshold voltage level converter for multi-VDD systems

Multiple voltage supply systems are most efficient and commonly employed techniques for low power designs. The idea behind this technique is to use multiple supply voltages (multi-V_DD) for a single chip by dividing the integrated circuit into regions, called voltage islands, operating at different voltages. In dual supply voltage circuits, when connecting a circuit having low voltage supply (V_DDL) to a circuit having high voltage supply (V_DDH), it is necessary to insert level converter at each low-to-high boundary as the interface to prevent the flow of static current. In this paper we have characterized the previously proposed Multi-Threshold voltage based level converters as well as proposed a new high performance level converter using Cadence Virtuoso tool in UMC 180nm standard CMOS technology. The proposed design offers up to 38.10% power reduction and up to 50.88% less Power Delay Product (PDP) than the existing level converters.